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| Back CS1088 Vacuum Fluorescent Display Tube Driver The VFD Driver is a microprocessor interface IC that drives a multiplexed VF (Vacuum Fluorescent) display tube. It consists of a 34-bit shift register, a 34-bit transparent data latch, a metal mask ROM, six 20 mA anode output drivers, twenty-five 2 mA anode output drivers, and three 50 mA grid drivers with output enables. Features Power On Reset Display Dimming Possible Three, 50 mA Grid Drivers Anodes: - 6 @ 20 mA - 25 @ 2 mA Chip Select Clock SPI Functions 5V GND Anodes 1:31 0.1 F VCC P PORT PORT PORT GND PORT DIN GRID1 CLK GRID2 STB GRID3 GREN GND VBB FILAMENT VFD GRID1GRID2 GRID3 GND http://onsemi.com * * * * 40 1 DIP-40 WIDE BODY N SUFFIX CASE 711 ORDERING INFORMATION* VIGN 12 V Device CS1088XN40 Package DIP-40 WIDE BODY Shipping 9 Units/Rail Regulator *For additional package options, consult your local ON Semiconductor sales office. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 7 of this data sheet. VBAT CS1088 Figure 1. Application Diagram (c) Semiconductor Components Industries, LLC, 2001 1 August, 2001 - Rev. 9 Publication Order Number: CS1088/D CS1088 MAXIMUM RATINGS* Parameter Supply Voltage (VBB) Input Voltages (DIN, CLK, STB, GREN) Junction Temperature Range Storage Temperature Range ESD Susceptibility (Human Body Model) ESD Susceptibility (Machine Model) Package Thermal Resistance, DIP-40 Junction-to-Case, RJC Junction-to-Ambient, RJA Lead Temperature Soldering: 1. 10 second maximum. 2. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Wave Solder (through hole styles only) Note 1 Reflow (SMD styles only) Note 2 Value -0.6 to +18 -0.6 to +6.0 -40 to +150 -55 to +150 2.0 200 20 45 260 Peak 230 Peak Unit V V C C kV V C/W C/W C ELECTRICAL CHARACTERISTICS (8.0 V VBB 16.5 V, Gnd = 0 V, -40C TJ 105C; unless otherwise stated. Note 3.) Parameter VBB Input VBB Input Voltage IBB0 Current Reset Mode DIN, CLK, STB Inputs VIL1, Input Low Voltage VIH, Input High Voltage IIL, Input Current GREN Input VIL, Input Low Voltage VIH, Input High Voltage IIH, Input Pull-down Current GRID1, GRID2, GRID3 Outputs IOL IOH VOL VOH AN24 - AN29 Outputs IOL IOH VOL VOH Sink Current Source Current IOUT = 400 A IOUT = -20 mA, VBB = 12 V 400 20 - VBB - 0.5 - - - - - - 0.5 VBB A mA V V Sink Current Source Current IOUT = 1.0 mA IOUT = -50 mA, VBB = 12 V 1.0 50 - VBB - 0.75 - - - - - - 0.5 VBB mA mA V V VIN = 3.325 V - - - 3.3 - - - 30 1.6 - 60 V V A VIN = VIH - - - 3.3 - - - 7.5 1.6 - 20.0 V V A - No outputs active, VBB = 16.5 V All outputs forced low. 8.0 - - - 2.0 6.5 16.5 5.0 7.5 V mA V Test Conditions Min Typ Max Unit 3. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production. http://onsemi.com 2 CS1088 ELECTRICAL CHARACTERISTICS (continued) (8.0 V VBB 16.5 V, Gnd = 0 V, -40C TJ 105C; unless otherwise stated. Note 4.) Parameter AN1 - AN23 Outputs IOL IOH VOL VOH Sink Current Source Current IOUT = 100 A IOUT = -2.0 mA, VBB = 12 V 100 2.0 - VBB - 0.5 - - - - - - 0.5 VBB A mA V V Test Conditions Min Typ Max Unit AC Characteristics: Input and Output Timing FC, CLK Frequency TCL, CLK Low Time TCH, CLK High Time TCR, CLK Rise Time TCF, CLK Fall Time TSC, STB Low to CLK High Time TST, STB High Time TAN, STB High to Anode Output Propagation Delay TGL, Grid Turn On Propagation Delay TG0, Grid Turn Off Propagation Delay TGR, Grid Rise Time TGF, Grid Fall Time TAR, Anode Rise Time TAF, Anode Fall Time VBB = 12 V VBB = 12 V At rated load. Note 5 At rated load. Note 5 At rated load. Note 5 At rated load. Note 5 - - - - - - - - 0 200 200 - - 50 500 - - - 0.50 0.35 0.40 0.40 - - - - - - - - - - - - - - 1.0 - - 100 100 - - 5.0 2.0 5.0 2.00 2.00 2.00 2.50 MHz ns ns ns ns ns ns s s s s s s s 4. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production. 5. Grid and anode rise / fall times are measured from 10% and 90% points. Output currents are at the maximum rated currents for the respective stages. http://onsemi.com 3 CS1088 PACKAGE LEAD DESCRIPTION Package Lead Number 40L DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Lead Symbol (31 Anode Configuration) GRID1 GRID2 GRID3 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 GND AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 DIN CLK STB GREN AN31 VBB 50 mA grid output. 50 mA grid output. 50 mA grid output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. Ground connection. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. 2.0 mA anode output. Shift register data input. Shift register clock input. Transfer contents of shift registers to output stages. Grid outputs enable. 2.0 mA anode output. Supply voltage input. Function http://onsemi.com 4 CS1088 GRID1 GRID2 GRID3 AN1 AN2 AN3 AN25 AN26 AN27 AN28 AN29 AN30 AN31 VBB POR GND VREG VREG VREG GREN VREG METAL MASK ROM STB DQ VREG LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DIN DQ CLK VREG R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R CLK Output Drive Capability Grid Outputs: 50 mA AN24 - AN29: 20 mA AN1 - AN23, AN30, AN31: 2.0 mA Figure 2. Block Diagram OPERATION DESCRIPTION Upon the initial application of power, the power on reset function will cause all of the anode and grid driver outputs to be off and all shift register outputs to be set low. Data is fed into the shift register through the DIN pin at the rising edge of the CLK input. Thirty four bits of data are capable of being stored by the shift register. Once the desired pattern is stored in the shift register, it can be transferred to the latch by setting the STB input high. The output of each latch drives its corresponding output stage. A logic high input to the shift register/latch will cause the corresponding output to turn on. A logic low input to the shift register/latch will cause the corresponding output to turn off. Please note that if the STB is held high, the outputs of the latch reflect the outputs of the corresponding shift register bits and will change if data is shifted in. The three GRID outputs are gated by the GREN input. When GREN is low, the GRID outputs are forced low regardless of the state of the corresponding latch output. When GREN is high, the GRID outputs correspond to the state of their respective latch outputs. The anode outputs, AN1 to AN31 are always enabled. http://onsemi.com 5 CS1088 APPLICATION INFORMATION Table 1. Bit Pattern, G = Grid, A = Anode. Bit # 1 G1 18 A15 2 G2 19 A16 3 G3 20 A17 4 A1 21 A18 5 A2 22 A19 6 A3 23 A20 7 A4 24 A21 8 A5 25 A22 9 A6 26 A23 10 A7 27 A24 11 A8 28 A25 12 A9 29 A26 13 A10 30 A27 14 A11 31 A28 15 A12 32 A29 16 A13 33 A30 17 A14 34 A31 Pin Name Bit # Pin Name 1 CLKIN DIN BIT 1 2 3 4 5 6 7 8 9 32 33 34 1 2 3 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 32 BIT 33 BIT 34 BIT 1 BIT 2 BIT 3 STB ANODES GREN GRIDS * * Selected grid goes high only if input bit pattern from shift register to grid is high. Figure 3. Typical Operation Unused grid and anode drivers should have their respective bits set to logic low in the data stream. Multiple grid or anode drivers may be connected together, but must be programmed to the same logic state for proper device operation. Maximum package power must be observed and care must be taken to maintian junction temperature below +150C. http://onsemi.com 6 CS1088 MARKING DIAGRAMS PIN CONNECTIONS 40 CS1088 AWLYYWW 1 DIP-40 WIDE BODY N SUFFIX CASE 711 40 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 7 GRID1 GRID2 GRID3 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 GND 1 VBB AN31 GREN STB CLK DIN AN30 AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 CS1088 PACKAGE DIMENSIONS DIP-40 WIDE BODY N SUFFIX CASE 711-03 ISSUE C 40 21 B 1 20 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 A N L C J H G F D K SEATING PLANE M ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 CS1088/D |
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